1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a structure of a multilevel interconnect.
2. Description of Related Art
The current integrated circuit device includes not only a field effect transistor (FET) and a bipolar device formed on the semiconductor substrate, but also a multilevel interconnect structure formed on the device. Different devices on the substrate can be connected by means of the multilevel interconnect structure. Among many integrated circuits, the multilevel interconnect structure extends in parallel with one or more arrays of conducting wires, while providing the function of the conducting wires in the devices formed by high integration stacking. When the size of the device is shrunk, an intermetal capacitance between the conducting wires obviously increases. As the data is transmitted with the conducting wires, unnecessary capacitive and inductive couplings are produced between the adjacent conducting wires in a narrow space. Such capacitive and inductive couplings reduce the speed for data transmission, especially during high-speed data transmission, while the increased energy consumption in this case also limits the efficiency of the device.
Referring to FIG. 1, an air gap 106 is formed in a dielectric layer between the conducting wires 102 on a substrate 100 in order to reduce the capacitive and inductive couplings between the multilevel interconnects. As the air has a smaller dielectric constant (about 1), the inter-metal dielectric (IMD) made with the air gap between the multilevel interconnects can reduce the dielectric constant and the capacitance between the parallel conducting wires, while improving the data transmission speed and the device efficiency.
Since a misalignment or an increase in critical dimension (CD) of an unlanded via opening (not shown) may occur during the formation of via opening 112, it is not easy to control an etching stopping point when the dielectric layers 110, 108, and 104 are made of similar materials. As a result, the via opening 112 can easily penetrate through the dielectric layers 110, 108, and 104, so that the air gap 106 is breached, resulting in an opening 106a extending form the via opening 112 and the air gap 106. The air gap 106 is not easily filled with a barrier layer 114, when the barrier layer 114 is formed by chemical vapor deposition (CVD) to cover the dielectric layer 110 and the profile of the via opening 112. Therefore, the reactant gas WF6 diffuses into the air gap 106 and reacts with the oxide in the dielectric layer, producing a poisoned via in the subsequent step for forming the tungsten plug (not shown).